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NOIV1SN025KA
The sensor can be in five different states:
Power-off
In this state, the sensor is inactive. All power supplies are
down and the power dissipation is zero.
Standby (1)
The registers below address 40 can be configured.
Standby (2)
In this standby state all SPI registers are active, meaning
that all SPI registers can be accessed for read and write
LVDS clock
reset_n
vddd_18
vddd_33
vdda_33
vdd_casc
other supplies
operations. All other blocks are disabled.
> 10us
> 10us
> 10us
> 10us
> 10us
> 10us
Note: An Intermediate Standby state is traversed after a
hard reset. In this state the sensor contains the default
configurations. Uploads of reserved registers are required to
traverse to the Standby (2) state
Idle
In the idle state, all sensor clocks are running and all
blocks are enabled, except the sequencer block. The sensor
is ready to start grabbing images as soon as the sequencer
block is enabled.
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in different
rolling/global master/slave modes.
Figure 13. Power ? up Procedure
NOTE: vdd_casc should come up prior to vdd_respd,
vdd_resfd, and vdd_trans.
The required input clock frequency depends on the word
depth mode of the sensor. This is possible in the following
mode:
? 8-bit
? 10-bit
The input clock frequencies to achieve a frame rate of
53 frames/s are listed in Table 7.
Table 7. CLOCK FREQUENCY OVERVIEW
User Actions: Functional Mode to Power Up
Sequences
Parameter
Input Clock Frequency
8 ? bit Mode
248 MHz
10 ? bit Mode
310 MHz
To ‘travel’ between the five possible states, a set of actions
is defined. Except for the power-up and power-down
sequences, all actions consist of a set of SPI uploads.
The “Sensor reconfiguration actions” indicated in
Figure 12 are used to reconfigure the operation modes of the
sensor. The sensor state itself is not altered.
Power-up Sequence
Figure 13 shows the power-up timing of the sensor. Apply
all power supplies in the order shown in the figure. It is
Enable Clock Management
The next step consists of SPI uploads which configures
the internal clock distribution. The required uploads are
listed in Table 8. It is important to follow the upload
sequence as listed.
Table 8. ENABLE CLOCK MANAGEMENT UPLOAD
No. Address Data Description
important to comply with the described sequence. Any
othyer supply ramping sequence may lead to high current
peaks and, as consequence, a failure of the sensor power up
When all the supplies are stable, enable the sensor clock
signal; then deassert the reset_n signal. After leaving the
1
2
3
2
32
34
0x0000
0x0001
0x2002
0x0001
NOIV1SN025KA
NOIV1SE025KA
Configure Clock Management
Enable Logic Blocks
hard-reset mode, the sensor enters the standby (1) state. To
go to the standby (2) mode, the sensor requires the
reconfiguration of some registers. This reconfiguration can
be applied 10 m s after the hard reset is released.
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